HELPING YOU DESIGN THE CHIP INSIDE Products and Solutions --- Solutions --- • Eclypse Low Power Solution • Galaxy Design Platform • Industry Solutions • Discovery Verification Platform • Synplicity FPGA Design Solution • Pilot Design Environment ---------- PRODUCTS ---------- BSD Compiler: Test synthesis Calibration Library CATS: Mask data preparation Circuit Check Circuit Explorer: Analysis & Optimization Confirma coreAssembler coreBuilder coreConsultant Custom Designer SE Custom Designer LE DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis DesignWare: Design & verif. IP DesignWare Virtual Platforms DFT Compiler MAX DFT Compiler: Test synthesis DSP Model Libraries: DSP algorithm design DSSA Sentry Enterprise: Layout editor ESP: Transistor-level Equivalence Checking Fammos TX Formality: Funct. equiv. checking Framework Hercules: Physical verification HSIM HSPICE: Accurate circuit simulation IC Compiler IC Workbench Plus Innovator: SoC / system modeling JupiterXT: Design planning Leda: RTL checker Liberty NCX: CCS Characterization Magellan: RTL formal verification Memory Solution Milkyway: Design database MVRC MVSIM NanoChar: 90 nanometer & below characterization NanoSim: Fast circuit simulation NanoTime Odyssey Defect/Odyssey YMS Paramos Pilot Design Environment Pioneer-NTB: SystemVerilog testbench automation Power Compiler: Power optimization PrimePower: Power analysis PrimeRail PrimeTime PX PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis PrimeYield Tool Suite Proteus OPC PSM-Create & PSM-Check Raphael Raphael NXT Recipe Manager and Editor (RME) Saber: Multi-tech. simulation Scirocco: VHDL simulation Seismos Sentaurus Device Sentaurus Lithography Sentaurus Process Sentaurus Structure Editor Sentaurus TFM Sentaurus Topography Sentaurus Workbench SiVL-LRC: Lithography verification SpiceCheck SpiceExplorer Star-RCXT: Full-chip RC extraction Star-RCXT VX Star-SimXT: Fast circuit simulation Synplify DSP: High-Level Algorithm System Studio: DSP algorithm design Taurus-Medici Taurus-TSuprem4 TetraMAX: ATPG VCS: Comprehensive RTL Verification VCS MX: Mixed-HDL simulation Vera: Testbench automation WaveView Analyzer XA Technology DESIGN IMPLEMENTATION VERIFICATION INTELLECTUAL PROPERTY DFM/TCAD DESIGN SERVICES CHINA  |  INDIA  |  KOREA  |  SINGAPORE  |  TAIWAN EVENTS TECHNICAL SUPPORT LOCATIONS & CONTACTS FEEDBACK SOLVNET SEARCH FOR IP SVP CAFE SYNOPSYS USERS GROUP Asia Pacific Events Calendar 2009-2010 Date Event Location Dec 15, 2009 CustomSim for Memory Timing & Power Analysis Webinar Jan 20, 2010 Addressing Signal Integrity Noise in Low Power Design Webinar CONTACT US  | LOCATIONS |  PRIVACY  |  LEGAL

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