Synopsys Asia Pacific - Singapore Training

HELPING YOU DESIGN THE CHIP INSIDE

Training

Date	Workshop	Cost USD/person
4-6 Jan 10	Design Compiler 1	US$1800
7-Jan 10	DC Topographical	US$600
11-12 Jan 10	HSIM	US$1200
13-15 Jan 10	Basic Verilog w/VCS	US$1800
25-27 Jan 10	DFT Compiler 1	US$1800
28-29 Jan 10	TetraMAX 1	US$1200
1-2 Feb 10	Low Power Flow HLD	US$1200
3-4 Feb 10	Low Power Flow PnR	US$1200
8-9 Feb 10	HSPICE Essential	US$1200
22-24 Feb 10	Design Compiler 1	US$1800
25-Feb-10	DC Topographical	US$600
1-3 Mar 10	System Verilog for TestBench	US$1800
8-10 Mar 10	PrimeTime 1	US$1800
11-Mar-10	PrimeTime Debugging	US$600
12-Mar-10	PrimeTime PX	US$600
15-17 Mar 10	Design Compiler 1	US$1800
18-Mar-10	DC Topographical	US$600
22-24 Mar 10	IC Compiler 1	US$1800
25-Mar-10	IC Compiler 2 CT	US$600
26-Mar-10	IC Compiler 2 HDP	US$600
6-8 Apr 10	DFT Compiler 1	US$1800
9-10 Apr 10	TetraMAX 1	US$1200
13-14 Apr 10	Low Power Flow HLD	US$1200
15-16 Apr 10	Low Power Flow PnR	US$1200
20-22 Apr 10	Design Compiler 1	US$1800
23-Apr-10	DC Topographical	US$600

** Synopsys reserves the right to cancel or re-schedule the workshops **
** Cancelled workshop

Please go to http://inter.viewcentral.com/reg/Synopsys/search and select the course listed in the table for course details.
Daily Class Time: 9.00am - 5.00pm

Advance Scheduling Workshop

Note: The following workshops require advanced scheduling and please contact sgp_training@synopsys.com for scheduling information:

Registration

City: Singapore
Please complete this Training registration form (PDF) and fax it to May Ang at (65) 62971272 or
Email: sgp_training@synopsys.com